[LIN, Jiunn-Horng 林俊宏, LIN, Jiunn-Horng 林俊宏, WANG, Jyh-Perng 王志鹏, LIN, Jiunn-Horng 林俊宏, WANG, Jyh-Perng 王志鹏, CHEN, Zeng-Weng 陈正文, LIN, Jiunn-Horng 林俊宏, WANG, Jyh-Perng 王志鹏, CHEN, Zeng-Weng 陈正文, FANG, Chien-Yu 方健宇, LIN, Jiunn-Horng 林俊宏, WANG, Jyh-Perng 王志鹏, CHEN, Zeng-Weng 陈正文, FANG, Chien-Yu 方健宇, ZENG, Hao-Zhen 曾晧真, LIN, Jiunn-Horng 林俊宏, WANG, Jyh-Perng 王志鹏, CHEN, Zeng-Weng 陈正文, FANG, Chien-Yu 方健宇, ZENG, Hao-Zhen 曾晧真, LAI, Jian-Fong 赖建逢, LIN, Jiunn-Horng 林俊宏, WANG, Jyh-Perng 王志鹏, CHEN, Zeng-Weng 陈正文, FANG, Chien-Yu 方健宇, ZENG, Hao-Zhen 曾晧真, LAI, Jian-Fong 赖建逢, HUANG, Weng-Zeng 黄文正, LIN, Jiunn-Horng 林俊宏, WANG, Jyh-Perng 王志鹏, CHEN, Zeng-Weng 陈正文, FANG, Chien-Yu 方健宇, ZENG, Hao-Zhen 曾晧真, LAI, Jian-Fong 赖建逢, HUANG, Weng-Zeng 黄文正, HSUAN, Shih-Ling 宣诗玲] No.1, Ln. 51, Dahu Road, Xiangshan Dist. 中国台湾省新竹市香山区大湖路51巷1号, Taiwan 300Hsinchu City, Taiwan 300 Disclosed are an expression element, an expression cassette, and a vector constructed thereby. The expression element has a promoting effect on the expression quantity of genes to be expressed, and thus has a highly industrial utilization value.

[Nai-Wen Fan, Shau-Yi Chen, Ai-Sen Liu, Zhi Zhong Ke, Chien-Bao Lin, Wen-Hao Zhuo, Feng-Zhi Chen, Chien-Cheng Kuo, Shih-Hao Chan, Chih-Hao Chen, Wei-Chih Peng, Chia-Liang Hsu] TW Hsinchu A thin-film deposition apparatus comprises a chamber; a carrier in the chamber; a showerhead on the carrier, wherein the showerhead comprises multiple first gas-dispensing holes, multiple second gas-dispensing holes and multiple plasma-generating portions; and a first gas inlet system for providing a first process gas, wherein the first process gas outputted from the multiple first gas-dispensing holes.

[Chien-Hao Chen, Hao-Ming Lien, Ssu-Yi Li, Jun-Lin Yeh, Kang-Cheng Lin, Kuo-Tai Huang, Chii-Horng Li, Chien-Hau Fei, Wen-Chih Yang, Jin-Aun Ng, Chi Hsin Chang, Chun Ming Lin, Harry Chuang, Chien-Liang Chen] TW Hsin-Chu The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.

[Ying-Hao WANG, Chien-Lung CHEN, Wei-Hao CHEN, Chien-Chi TZENG, Hu-Wei LIN] TW Hsinchu An under boat support (UBS) includes an electrostatic discharge (ESD) safe ceramic body and a conductive body. The ESD safe ceramic body is coupled to a surface of the conductive body by an adhesive, which may be resistant to high temperatures. A plurality of springs are present within the adhesive and extend from the surface of the conductive body to a surface of the ESD safe ceramic body. For example, first ends of the plurality of springs are electrically coupled to the surface of the conductive body, and second ends of the plurality of springs, which are opposite to corresponding ones of the first ends of the plurality of springs, are electrically coupled to the surface of the ESD safe ceramic body. The plurality of springs form electrical pathways such that the ESD safe ceramic body is electrically coupled to the conductive body.

[Chien-Hao Chen, Hao-Ming Lien, Ssu-Yu Li, Jun-Lin Yeh, Kang-Cheng Lin, Kuo-Tai Huang, Chii-Horng Li, Chien-Liang Chen, Chung-Hau Fei, Wen-Chih Yang, Jin-Aun Ng, Chi Hsin Chang, Chun Ming Lin, Harry Chuang] TW Chungwei Township, Ilan County The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.

[Chien-Hao Chen, Hao-Ming Lien, Ssu-Yi Li, Jun-Lin Yeh, Kang-Cheng Lin, Kuo-Tai Huang, Chii-Horng Li, Chien-Liang Chen, Chung-Hau Fei, Wen-Chih Yang, Jin-Aun Ng, Chi Hsin Chang, Chun Ming Lin, Harry Chuang] TW Hsin-Chu The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.

[CHEN CHIEN-HAO, LIEN HAO-MING, LI SSU-YI, LI CHII-HORNG, CHEN CHIEN-LIANG, FEI CHUNG-HAU, YANG WEN-CHIH, NG JIN-AUN, CHANG CHI-HSIN, LIN CHUN-MING, CHUANG HARRY, YEH JUN-LIN, LIN KANG-CHENG, HUANG KUO-TAI] TW The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with outer edge of the sealing layer.

[CHEN CHIEN HAO, LIEN HAO MING, LI SSU YI, LI CHII HORNG, CHEN CHIEN LIANG, FEI CHUNG HAU, YANG WEN CHIH, NG JIN-AUN, CHANG CHI HSIN, LIN CHUN MING, CHUANG HARRY, YEH JUN LIN, LIN KANG CHENG, HUANG KUO TAI] TW

[WANG YING-HAO, CHEN WEI-HAO, TZENG CHIEN-CHI, CHEN CHIEN-LUNG, LIN HU-WEI] TW An under boat support (UBS) includes an electrostatic discharge (ESD) safe ceramic body and a conductive body. The ESD safe ceramic body is coupled to a surface of the conductive body by an adhesive, which may be resistant to high temperatures. A plurality of springs are present within the adhesive and extend from the surface of the conductive body to a surface of the ESD safe ceramic body. For example, first ends of the plurality of springs are electrically coupled to the surface of the conductive body, and second ends of the plurality of springs, which are opposite to corresponding ones of the first ends of the plurality of springs, are electrically coupled to the surface of the ESD safe ceramic body. The plurality of springs form electrical pathways such that the ESD safe ceramic body is electrically coupled to the conductive body.

[WU CHAU-CHUNG, LIN FANG-JU, LIN CHING-PO, KUO CHEN-YUAN, HSIAO YU-CHUNG, WANG SHOEI-SHEN, WANG TZUNG-DAU, WANG KUO-YANG, CHU CHUN-YUAN, WU YU-SHENG, WU CHO-KAI, WU YEN-WEN, SUNG SHIH-HSIEN, LEE JEN-KUANG, LEE MEI-YUEH, LEE YI-HENG, LIN TSUNG-HSIEN, LIN CHENG-JUI, LIN LIANG-YU, LIN MAO-HSING, HSUAN CHIN-FENG, HUNG SHIH-YUAN, HU CHI-MING, YIN WEI-HSIAN, KAO HSIEN-LI, CHANG KUAN-CHENG, CHANG WEI-TIEN, CHEN WEN-JONE, CHEN YEN-YUAN, CHEN YIH-SHARNG, CHEN JAW-WEN, TSENG WEI-KUNG, HO LI-TING, HUANG CHIN-CHOU, HUANG CHIEN-HUA, HUANG PO-HSUN, YANG KAI-CHIEN, YEH HUNG-I, YEH CHIH-FAN, CHU PAO-HSIEN, LIU PING-YEN, CHENG HAO-MIN, HSIEH I-CHANG] TW