[YAMASHITA, Chikamasa 山下　親正, YAMASHITA, Chikamasa 山下　親正, OKA, Jun-Ichiro 岡　淳一郎, YAMASHITA, Chikamasa 山下　親正, OKA, Jun-Ichiro 岡　淳一郎, HORIGUCHI, Michiko 堀口　道子, YAMASHITA, Chikamasa 山下　親正, OKA, Jun-Ichiro 岡　淳一郎, HORIGUCHI, Michiko 堀口　道子, SASAKI-HAMADA, Sachie 濱田　幸恵] 1-3, Kagurazaka, Shinjuku-ku, Tokyo 〒1628601 東京都新宿区神楽坂一丁目３番地 Tokyo1628601 　Provided are: a centrally-acting peptide derivative having a central action portion, a transmembrane sequence portion, and an endosome escape portion; and a pharmaceutical composition including the same.

[MORIE, Kyoko 森江　恭子, MORIE, Kyoko 森江　恭子, SHINADA, Atsuko 品田　敦子, MORIE, Kyoko 森江　恭子, SHINADA, Atsuko 品田　敦子, HORIGUCHI, Hirofumi 堀口　博文, MORIE, Kyoko 森江　恭子, SHINADA, Atsuko 品田　敦子, HORIGUCHI, Hirofumi 堀口　博文, YOSHIKAWA, Jun 吉川　潤] 6-2-10 Ginza, Chuo-ku, Tokyo 〒1040061 東京都中央区銀座６－２－１０ Tokyo1040061 [Problem] The purpose is to produce fermented milk containing lactic acid bacteria and bifidobacteria while increasing and maintaining the number of live bifidobacteria by a simple method. [Solution] A method for producing fermented milk that conducts in order a first step for mixing raw material milk, lactic acid bacteria, and bifidobacteria and a second step for fermenting the raw material milk, wherein the method for producing fermented milk is characterized by having a step for adding lactase to the raw material milk before completing the second step and conducting a lactase addition step at one or more times selected from before the first step, substantially simultaneously with the first step, or after the first step. [Problem] The purpose is to produce fermented milk containing lactic acid bacteria and bifidobacteria while increasing and maintaining the number of live bifidobacteria by a simple method. [Solution] A method for producing fermented milk that conducts in order a first step for mixing raw material milk, lactic acid bacteria, and bifidobacteria and a second step for fermenting the raw material milk, wherein the method for producing fermented milk is characterized by having a step for adding lactase to the raw material milk before completing the second step and conducting a lactase addition step at one or more times selected from before the first step, substantially simultaneously with the first step, or after the first step.

[SATO, Tomoko 佐藤　智子, SATO, Tomoko 佐藤　智子, YOSHIKAWA, Jun 吉川　潤, SATO, Tomoko 佐藤　智子, YOSHIKAWA, Jun 吉川　潤, HORIGUCHI, Hirofumi 堀口　博文] 6-2-10 Ginza, Chuo-ku, Tokyo 〒1040061 東京都中央区銀座６－２－１０ Tokyo1040061 [Problem] To provide a lactase solution having excellent thermal stability. [Solution] A lactase solution, wherein the proportion of a lactase fraction having a molecular weight of approximately 120 kDa according to SDS polyacrylamide gel electrophoresis is 20% or greater.

[AMACHI, Seigo 天知　誠吾, AMACHI, Seigo 天知　誠吾, YOSHIKAWA, Jun 吉川　潤, AMACHI, Seigo 天知　誠吾, YOSHIKAWA, Jun 吉川　潤, HORIGUCHI, Hirofumi 堀口　博文] 1-33, Yayoi-cho, Inage-ku, Chiba-shi, Chiba 〒2638522 千葉県千葉市稲毛区弥生町１番３３号 Chiba2638522;2-10, Ginza 6-chome, Chuo-ku, Tokyo 〒1048162 東京都中央区銀座６丁目２番１０号 Tokyo1048162 Provided is a new composition for decolorizing a dye. This composition for decolorizing a dye contains a multicopper oxidase and iodide ions.

[SATO, Tomoko, YOSHIKAWA, Jun, HORIGUCHI, Hirofumi] 2-10 Ginza 6-chome Chuo-ku, Tokyo 104-8162, JP [Problem]To provide a lactase solution having excellent thermal stability.[Solution]A lactase solution in which the ratio of a lactase fraction having a molecular weight of about 120 kDa measured by SDS polyacrylamide gel electrophoresis is 20% or more.

[Kiyohara, Kunio, Kuwano, Yohei, Horiguchi, Kazuaki, Katakabe, Jun] 184-1 Maioka-cho, Totsuka-ku, Yokohama-shi, Kanagawa, 244-8522, JP A cup holder device (1) includes a fixed case (2), a movable case (3) capable of moving between a stored position stored in the fixed body and a drawn-out position projecting forward from an opening of the fixed body, and a cup holder (4) capable of moving between a stored position stored in the movable case and a use position projecting forward from an opening of the movable case. A coupling member (8) is provided on the movable case and pivotally supported such that a projection (12) at one end engages the cup holder in the stored position and a claw (10) at the other end engages the fixed case in the drawn-out position. The coupling member is normally urged toward the fixed case. ＜img id="iaf01" file="imgaf001.tif" wi="78" he="86" img-content="drawing" img-format="tif" /＞

[Horiguchi Masashi(Kawasaki,JPX), Etoh Jun(Hachioji,JPX), Aoki Masakazu(Tokorozawa,JPX), Itoh Kiyoo(Higashikurume,JPX)] A redundancy technique is introduced for a semiconductor memory and, more particularly a redundancy technique for a dynamic random access memory (DRAM) having a storage capacity of 16 mega bits or more. In such a DRAM, the efficiency of the redundancy technique is reduced, since a memory array is divided into a large number of memory mats. According to the present redundancy technique, in a semiconductor memory including a memory array which has a plurality of word lines, a plurality of bit lines arranged so that two-level crossings are formed between the word lines and the bit lines, and memory cells disposed at desired ones of the two-level crossings, there is provided, furthermore, a plurality of spare word (or bit) lines, address comparing circuits for storing therein a defective address existing in the memory array, to compare an address to be accessed with the defective address, and selection circuitry for replacing a word or bit line including a defective memory cell by a spare word (or bit) line in accordance with the result of the comparison. The memory array of the semiconductor memory is divided into M memory mats (where M .gtoreq.2), the number m of word or bit lines which are simultaneously replaced by spare word (or bit) lines, is less than the number M and equal to a divisor thereof, and the number L of spare word (or bit) lines per one memory mat and the number R of address comparing circuits satisfy a relation L＜R.ltoreq.LM/m and, preferably, L＜R＜LM/m.

[Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata] ,Iruma,,;,Iruma,,;,Ohme,,;,Ohme,,;,Ohme,,;,Machida,,;,Kokubunji,,;,Tokyo,,;,Higashiyamato,,;,Akishima,,;,Akishima,,;,Tokorozawa,,;,Tokorozawa,,;,Akishima,,;,Tokyo,,;,Ohme,,;,Tokyo,,;,Hachioji,,;,Tokyo,,;,Hachioji,,;,Kawasaki,,;,Koganei,,;,Kodaira,, Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

[HINODE TAIKI, OTA TAKASHI, HORIGUCHI HIROSHI, SAWASHIMA JUN, FUKATSU EIJI, HASHIMOTO KOJI] JP

[KAWASE YASUSHI, HORIGUCHI SHINJI, TANAKA HITOSHI, IKENAGA SHINICHI, ETO JUN, AOKI MASAKAZU, ITO KIYOO] ;; PURPOSE:To obtain internal voltage generation circuits which are less in noise, small in occupying area, and low in power consumption by causing plural internal circuits to selectively operate by means of control signals and at least two internal circuits which do not operate simultaneously to share one internal voltage generating circuit. CONSTITUTION:Internal voltage generating circuit 3-5 and load circuits, such as pulse generating circuit 6-9, etc., using the outputs of the circuits 3-5 are arranged closely to each other and two load circuits which have a selected- nonselected relation between them about an address signal ai, etc., share one internal voltage generating circuits. Since the load circuits are provided closely to the internal voltage generating circuits 3-5, the impedance of the wirings can be reduced and, as a result, the level of produced noises can be suppressed. Moreover, since two load circuits having a selected-nonselected relation between them about the address signal ai share one internal voltage generating circuit, the chip occupying area and power consumption of the circuit can be reduced.