[GLADWIN MARK T, SCHECHTER ALAN N, LEFER DAVID J, PATEL RAKESH P, HUNTER CHRISTIAN J, POWER GORDON G] US;US;US;US;US It has been surprisingly discovered that administration of nitrite to subjects causes a reduction in blood pressure and an increase in blood flow to tissues. The effect is particularly beneficial, for example, to tissues in regions of low oxygen tension. This discovery provides useful treatments to regulate a subject\'s blood pressure and blood flow, for example, by the administration of nitrite salts. Provided herein are methods of administering a pharmaceutically-acceptable nitrite salt to a subject, for treating, preventing or ameliorating a condition selected from: (a) ischemia-reperfusion injury (e.g., hepatic or cardiac or brain ischemia-reperfusion injury); (b) pulmonary hypertension (e.g., neonatal pulmonary hypertension); or (c) cerebral artery vasospasm.

[SCHECHTER ALAN N, POWER GORDON G, PATEL RAKESH P, OLDFIELD EDWARD H, HUNTER CHRISTIAN J, LEFER DAVID J, CANNON RICHARD O III, PLUTA RYSZARD, GLADWIN MARK T, KIM-SHAPIRO DANIEL B] US;US;US;US;US

[Mark T. Gladwin, Daniel B. Kim-Shapiro, Rakesh P. Patel, Jeffrey Kerby] US MD Rockville This disclosure relates to methods of using nitrite to detoxify stroma-free hemoglobin based blood substitutes. In particular, methods are described for using a blood substitute comprised of about equimolar amounts of nitrite and hemoglobin (e.g., nitrite-metHb) to treat, prevent, or ameliorate diseases of the blood in a subject, or as a blood replacement in a subject.

[Kevin A. Norman, Rakesh H. Patel, Stephen P. Sample, Michael R. Butts] CA San Jose A programmable logic device architecture. This programmable logic architecture includes a first logic block (425) containing programmable logic elements for performing logic functions. The architecture may also include a diagnostic block interface (415), which interfaces with the first logic block (425), for performing JTAG functions, configuring the first logic block (425), initializing the first logic block (425), interfacing with off-chip diagnostic and test devices and equipment, and performing other similar functions. The first logic block (425) may be programmably coupled to other components on the integrated circuit using a first programmable interconnect network (511). The first logic block (425) includes a plurality of second logic blocks (505) which may be programmably coupled using a second programmable interconnect network (521). The second programmable interconnect network (521) may be programmably coupled to the first programmable interconnect network (511). Furthermore, the plurality of second logic blocks (505) include a plurality of third logic blocks (525) which may be programmably coupled using a third programmable interconnect network (535). A signal from a third logic block (525) may be programmably coupled to the other logic blocks, the diagnostic block interface (415), and other circuitry on the integrated circuit. The internal circuitry of these logic blocks may be monitored through a variety of programmable interconnect paths. This architecture is useful when debugging a design, especially for emulation and prototyping applications.

[Stephen P. Sample, Michael R. Butts, Kevin A. Norman, Rakesh H. Patel] CA San Jose An overcurrent protection circuit for input/Output (I/O) buffers for a Field Programmable Gate Array wherein short circuits can be detected and the output current limited so as to avoid damaging the device. I/O buffers having the overcurrent protection circuit can detect a contention between the buffers. In order to eliminate the contention, certain I/O buffers will go into a noncontending state.

[GUSTOW, Evan, E., RYDE, Tuula, A., RUDDY, Stephen, B., JAIN, Rajeev, PATEL, Rakesh, WILKINS, Michael, John, RYDE, Niels, P.] Monksland, Athlone County Westmeath, IE

[Sample Stephen P.(Saratoga,CA), Butts Michael R.(Portland,OR), Norman Kevin A.(Belmont,CA), Patel Rakesh H.(Cupertino,CA)] An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array ("FPGA"), as described herein has flexible input/output buffer circuits. These input/output buffer circuits transfer data either bidirectionally or unidirectionally between an input/output pin and a FPGA core. Each input/output buffer circuit allows at least two signals to be time-multiplexed onto an input/output pin thereby doubling the effective input/output capacity. The input/output buffer circuits may be used to time-multiplex at least two signals onto an input pin, at least two signals onto an output pin, or both. Each input/output buffer circuit further has shared flip flops for time-multiplexing signals. The circuitry provides two connections into the FPGA core which can be used to time-multiplex at least two independent inputs or outputs.

[Mark T. Gladwin, Daniel B. Kim-Shapiro, Rakesh P. Patel, Jeffrey Kerby] US PA Pittsburg This disclosure relates to methods of using nitrite to detoxify stroma-free hemoglobin based blood substitutes. In particular, methods are described for using a blood substitute comprised of about equimolar amounts of nitrite and hemoglobin (e.g., nitrite-metHb) to treat, prevent, or ameliorate diseases of the blood in a subject, or as a blood replacement in a subject.

[Stephen P. Sample, Michael R. Butts, Kevin A. Norman, Rakesh H. Patel] CA San Jose An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array ("FPGA"), as described herein has flexible input/output buffer circuits. These input/output buffer circuits transfer data either bidirectionally or unidirectionally between an input/output pin and a FPGA core. Each input/output buffer circuit allows at least two signals to be time-multiplexed onto an input/output pin thereby doubling the effective input/output capacity. The input/output buffer circuits may be used to time-multiplex at least two signals onto an input pin, at least two signals onto an output pin, or both. Each input/output buffer circuit further has shared flip flops for time-multiplexing signals. The circuitry provides two connections into the FPGA core which can be used to time-multiplex at least two independent inputs or outputs.

[Stephen P. Sample, Michael R. Butts, Kevin A. Norman, Rakesh H. Patel, Chao Chiang Chen] CA San Jose An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array ("FPGA"), as described herein has multiple blocks of multi-ported memory. The memory has a plurality of read ports and a plurality of write ports. Each port of the multi-ported memory can be configured with a width and depth that is independent and separate from the width and depth of the other ports. The memory also includes a port for taking a synchronous snapshot of the contents of the memory or for loading the memory to an initial state. The memory shares routing lines used by a low level logic element thereby alleviating the need to add routing lines to an interconnect network just to satisfy the memory requirements.