[Tsuoe-Hsiang Liao, Bing-Yao Fan, Yi-Ju Liu] TW Hsinchu A lateral diffused metal-oxide-semiconductor field-effect transistor structure including a P substrate, an N+ buried layer, an N epitaxial layer, a P well, an N well, a drain region, a source region, and a body region is disclosed. The N+ buried layer is located between the P substrate and the N epitaxial layer, the P well contacts the N+ buried layer, the source region and the body region are located in the P well, the N well is located in the N epitaxial layer, and the drain region is located in the N well. When a high voltage is applied to the drain and the P substrate is grounded, a breakdown voltage with the P substrate is raised because of the N+ buried layer isolating the P substrate from the N epitaxial layer, so as to be able to avoid PN junction breakdown.

[LIAO TSUOE-HSIANG] TW Method for realizing circuit layouts. Complex integrated circuit includes cells of basic functions, and layout designs for these cells can be recorded as a library. The claimed invention replaces common power strips with grid power contact/via in layout of each cell. While realizing layout of an integrated circuit, a routing procedure is used to connect power of all cells arranged in the integrated circuit. Because power strip is avoided in each cell, the claimed invention can reduce layout height of each cell, and therefore increase integrity of integrated circuits.

[Tsuoe-Hsiang Liao, Bing-Ling Fan, Chwai-San Tseng] TW Hsinchu A sound effect power supply configuration includes a USB power supply source, an external audio source, a sound effect unit and an external speaker, wherein the USB power input terminal provides sound effect unit USB power source, for the sound effect unit after obtaining USB power source may receive the audio signals output by the external audio source, and after appropriately processing the audio, may drive the external speaker to generate sounds having high quality sound effect.

[Tsuoe-Hsiang Liao] TW Hsin-Chu City A method for realizing circuit layouts. Complex integrated circuit includes cells of basic functions, and layout designs for these cells can be recorded as a library. The claimed invention replaces common power strips with grid power contacts/vias in the layout of each cell. While realizing the layout of an integrated circuit, a routing procedure is used to connect power of all cells arranged in the integrated circuit. Because power strips are avoided in each cell, the claimed invention can reduce layout height of each cell, and therefore increase integration of integrated circuits.

[Tsuoe-Hsiang Liao] TW Hsin-Chu A method for realizing circuit layouts. Complex integrated circuit includes cells of basic functions, and layout designs for these cells can be recorded as a library. The claimed invention replaces common power strips with grid power contacts/vias in the layout of each cell. While realizing the layout of an integrated circuit, a routing procedure is used to connect power of all cells arranged in the integrated circuit. Because power strips are avoided in each cell, the claimed invention can reduce layout height of each cell, and therefore increase integration of integrated circuits.

[Tsuoe-Hsiang Liao, Huo-Tieh Lu, Yu-Fang Chien, Chih-Chien Liu, Pei-Lin Kuo, Yu-Ru Yang] TW Hsin-Chu City A capacitor structure has a first electrode and a second electrode, which does not electrically connect to the first electrode. The first electrode has a plurality of first meshed conductive structures. The first meshed conductive structures have the same layout pattern, and are electrically connected to each other. The second electrode has a plurality of second meshed conductive structures. The second meshed conductive structures have the same layout pattern, and are electrically connected to each other. The first meshed conductive structures and the second meshed conductive structures are alternately stacked.

[Liao Tsuoe-Hsiang(Hsinchu,TWX)] A charge pumping circuit generates a negative voltage equal in magnitude to the positive supply voltage. A non-overlapping clock is used to set the voltage across a first capacitor equal to the positive supply voltage through a MOS switch. This stored voltage is then transferred to a second capacitor through a second MOS switch to generate a negative voltage at one terminal of the second MOS switch. The use of MOS switches eliminates the threshold voltage drop if MOS diodes were used to charge the first capacitor or to transfer the voltage from the first capacitor to the second capacitor.

[LIAO TSUOE HSIANG] TW

[Tsuoe-Hsiang Liao] TW Hsinchu City 300 A layout structure of semiconductor cells is described. The layout structure includes multiple semiconductor cells, wherein at least one pair of cells has an overlap member part between them, so that the area of the pair of cells is smaller than the sum of respective areas of the two cells.

[Ming-Te Lin, Tsuoe-Hsiang Liao] TW Chutung A cell arrangement scheme is disclosed. A first cell comprising a PMOS and a NMOS, wherein the source of the PMOS is connected with a power line VDD by a first metal line, the source of the NMOS is connected to a power line GND by a second, the drains of the PMOS and NMOS connected together by a third metal line, and the gate of the PMOS and the NMOS are connected together by a poly line. A second cell comprising a PMOS and a NMOS, wherein the source of the PMOS is connected with a power line VDD by a first metal line, the source of the NMOS is connected to a power line GND by a second metal line, the drains of the PMOS and NMOS connected together by a third metal line, and the gate of the PMOS and the NMOS are connected together by a poly line. Partially overlapping the first cell in a such a way that the first and the second metal line of the first cell is overlapped and in contact with the first and the second metal line of the second cell respectively. The cells are positioned so as to minimize the block size so that the total area of the layout can be minimized.