in:(WANG JI-FENG)

Grading system and application of hydrogenation catalyst and grading method of hydrogenation catalyst TW111140247A
[YANG ZHAN-LIN, DING SI-JIA, LIU YI, PENG SHAO-ZHONG, WANG HUI-GANG, JIANG HONG, WANG JI-FENG, WANG FANG-ZHAO, WANG PING] CN The present invention relates to the field of oil product hydrogenation, and relates to a grading system and an application of a hydrogenation catalyst and a grading method of the hydrogenation catalyst. The system comprises M hydrogenation catalysts sequentially filled in a material flow direction, wherein M is an integer greater than 2; an R value of an Nth hydrogenation catalyst is not less than an R value of an (N-1)th hydrogenation catalyst, and the R value of at least one Nth hydrogenation catalyst is greater than the R value of the (N-1)th hydrogenation catalyst, wherein N is an integer greater than 2 and not greater than M; the R value is a ratio of molar content of the VIII group metal element in the hydrogenation catalyst characterized by an X-ray photoelectron spectrum to weight content of the VIII group metal element in terms of oxides in the hydrogenation catalyst characterized by an X-ray fluorescence spectrum. According to the grading system of the hydrogenation catalyst provided in the present invention, the hydrogenation catalysts having different surface nickel atom concentrations are used for grading, thereby facilitating improving the overall denitrification effect of the device, and improving the hydrogenation saturation performance of a catalyst system.
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TW111140247A
[YANG ZHAN-LIN, DING SI-JIA, LIU YI, PENG SHAO-ZHONG, WANG HUI-GANG, JIANG HONG, WANG JI-FENG, WANG FANG-ZHAO, WANG PING] CN
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Semiconductor structure and method of forming the same TW107128251A
[CHEN JUN, HUA ZI QUN, HU SI-PING, WANG JIA-WEN, WANG TAO, ZHU JI-FENG, DING TAO-TAO, WANG XIN-SHENG, ZHU HONGBIN, CHENG WEIHUA, YANG SIMON SHI-NING] CN The present invention relates to a semiconductor structure and method of forming the same. The semiconductor structure includes a first substrate, a first bonding layer on the surface of first substrate, the material of first bonding layer includes dielectrics such as Si, N and C, and the first bonding layer of semiconductor structure is provided with higher bonding force in wafer bonding.
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Semiconductor structure and method of forming the same TW107128246A
[CHEN JUN, HUA ZI QUN, HU SI-PING, WANG JIA-WEN, WANG TAO, ZHU JI-FENG, DING TAO-TAO, WANG XIN-SHENG, ZHU HONGBIN, CHENG WEIHUA, YANG SIMON SHI-NING] CN The present invention relates to a semiconductor structure and method of forming the same. The semiconductor structure includes a first substrate, a first adhesive /bonding stack on the surface of first substrate, wherein the first adhesive/bonding stack includes at least one first adhesive layer and at least one first bonding layer. The material of first bonding layer includes dielectrics such as Si, N and C, the material of first adhesive layer includes dielectrics such as Si and N, and the first adhesive/bonding stack of semiconductor structure is provided with higher bonding force in wafer bonding.
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Hybrid bonding using dummy bonding contacts TW108108380A
[WANG TAO, HU SI-PING, WANG JIA-WEN, HAUANG SHI-QI, ZHU JI-FENG, CHEN JUN, HUA ZI QUN] CN A semiconductor device including a first semiconductor structure bonded to and second semiconductor structure is disclosed. The first semiconductor structure includes a first interconnecting layer having a plurality of first interconnecting structures and a first bonding layer having a plurality of first bonding contacts. Each first interconnecting structure is connected to a corresponding one of the first bonding contacts. The second semiconductor structure includes a second interconnecting layer having a plurality of second interconnecting structures and a second bonding layer having a plurality of second bonding contacts. At least one of the second bonding contacts is connected to a corresponding one of the second interconnecting structures, and at least another one of the second bonding contacts is separated from each of the second interconnecting structures. A bonding surface is dislosed between the first bonding layer and the second bonding layer. Each first bonding contact is connected to a corresponding one of the second bonding contacts at the bonding surface.
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LED TUBE LAMP US17871006
[Guang-Dong Wang, Ji-Feng Xu, Ming-Bin Wang, Zi-Xiang Zou, Dong-Mei Zhang] CN Jiaxing An LED tube lamp includes a first and second members and a connection member. Each of the first and second members includes lighting part and an end part. Each lighting part includes LED light strip. The connection member includes electrical connection portions and joining portions for the first and second members. The connection member connects the first member with the second member by the joining portions and the electrical connection portions and makes the first member substantially coaxial to the second member.
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LED tube lamp US17871006
[Guang-Dong Wang, Ji-Feng Xu, Ming-Bin Wang, Zi-Xiang Zou, Dong-Mei Zhang] CN Jiaxing An LED tube lamp includes a first and second members and a connection member. Each of the first and second members includes lighting part and an end part. Each lighting part includes LED light strip. The connection member includes electrical connection portions and joining portions for the first and second members. The connection member connects the first member with the second member by the joining portions and the electrical connection portions and makes the first member substantially coaxial to the second member.
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Hybrid bonding using dummy bonding contacts and dummy interconnecting structures TW108108365A
[WANG TAO, HU SI-PING, WANG JIA-WEN, HAUANG SHI-QI, ZHU JI-FENG, CHEN JUN, HUA ZI QUN] CN A semiconductor device including a first semiconductor structure bonded to and second semiconductor structure is disclosed. The first semiconductor structure includes a first interconnecting layer and a first bonding layer respectively having a plurality of first interconnecting structures and a plurality of first bonding contacts. Each first interconnecting structure is connected to a corresponding one of the first bonding contacts. At least one of the first interconnecting structures is a first dummy interconnecting structure. The second semiconductor structure includes a second interconnecting layer and a second bonding layer respectively having a plurality of second interconnecting structures and a plurality of second bonding contacts. Each second interconnecting structure is connected to a corresponding one of the second bonding contacts. At least one of the second interconnecting structures is a second dummy interconnecting structure. A bonding surface is dislosed between the first bonding layer and the second bonding layer. Each first bonding contact is connected to a corresponding one of the second bonding contacts at the bonding surface.
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ASSISTED WRITE METHOD FOR MAGNETIC RANDOM ACCESS MEMORY KR20190083708A
[YING JI FENG, WANG JHONG SHENG, HOU DUEN HUEI] TW Provided is a method for recording to a magnetic random access memory cell which comprises the steps of: applying an alternating signal to a magnetic random access memory cell having a first magnetic orientation; and applying a direct current pulse to the magnetic random access memory cell in order to change a magnetic orientation of the magnetic random access memory cell from the first magnetic orientation to a second magnetic orientation. The first magnetic orientation and the second magnetic orientation are different.
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Methods for forming three-dimensional memory devices TW107129067A
[ZHU JI-FENG, CHEN JUN, LU ZHENYU, TAO QIAN, HU SI-PING, WANG JIA-WEN, FU YANG] CN Embodiments of methods for forming three-dimensional (3D) memory devices are disclosed. In an example, a peripheral device is formed on a first substrate. A first interconnect layer is formed above the peripheral device on the first substrate. A dielectric stack including a plurality of dielectric/sacrificial layer pairs and a plurality of memory strings each extending vertically through the dielectric stack is formed on a second substrate. A second interconnect layer is formed above the memory strings on the second substrate. The first substrate and the second substrate are bonded, so that the first interconnect layer is below and in contact with the second interconnect layer. The second substrate is thinned after the bonding. A memory stack is formed below the thinned second substrate and including a plurality of conductor/dielectric layer pairs by replacing, with a plurality of conductor layers, sacrificial layers in the dielectric/sacrificial layer pairs.
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