[Zhiwei Liu, Juin J. Liou, James E. Vinson] US CA Milpitas A silicon-controlled rectifier (SCR) device having a high holding voltage includes a PNP transistor and an NPN transistor, each transistor having both p-type and n-type dopant regions in their respective emitter areas. The device is particularly suited to high voltage applications, as the high holding voltage provides a device which is more resistant to latchup subsequent to an electrostatic discharge event compared to devices having a low holding voltage.

[Javier A. Salcedo, Juin J. Liou, Joseph C. Bernier, Donald K. Whitney] US CA Milpitas Symmetrical/asymmetrical bidirectional S-shaped I-V characteristics with trigger voltages ranging from 10 V to over 40 V and relatively high holding current are obtained for advanced sub-micron silicided CMOS (Complementary Metal Oxide Semiconductor)/BiCMOS (Bipolar CMOS) technologies by custom implementation of P1-N2-P2-N1//N1-P3-N3-P1 lateral structures with embedded ballast resistance 58, 58A, 56, 56A and periphery guard-ring isolation 88-86. The bidirectional protection devices render a high level of electrostatic discharge (ESD) immunity for advanced CMOS/BiCMOS processes with no latchup problems. Novel design-adapted multifinger 354/interdigitated 336 layout schemes of the ESD protection cells allow for scaling-up the ESD performance of the protection structure and custom integration, while the I-V characteristics 480 are adjustable to the operating conditions of the integrated circuit (IC). The ESD protection cells are tested using the TLP (Transmission Line Pulse) technique, and ESD standards including HBM (Human Body Model), MM (Machine Model), and IEC (International Electrotechnical Commission) IEC 1000-4-2 standard for ESD immunity. ESD protection performance is demonstrated also at high temperature (140° C.). The unique high ratio of dual-polarity ESD protection level per unit area, allows for integration of fast-response and compact protection cells optimized for the current tendency of the semiconductor industry toward low cost and high density-oriented IC design. Symmetric/asymmetric dual polarity ESD protection performance is demonstrated for over 15 kV HBM, 2 kV MM, and 16.5 kV IEC for sub-micron technology.

[GASNER, John, T., CHURCH, Michael, D., PARAB, Sameer, BAKEMAN, Paul, E., Jr., DECROSTA, David, A., LOMENICK, Robert, L., MCCARTY, Chris, A.] 375 Trade Zone Blvd., Milpital, CA 95035, US

[Walters, Michael M.] 1001 Murphy Ranch Road, Milpitas, CA 95035, US A converter system (100) including a cascade boost converter (103) and inverting buck converter (105) and controller (101) for converting a rectified AC voltage (VR) to a DC output current (ILD). The system uses inductors (L1,L2) and is configured to use a common reference voltage (REF). The controller is configured to control switching of the converters (103,105) in an independent manner to decouple operation from each other. For example, control pulses for the boost converter (103) may be wider than pulses for the buck (104) converter. The controller (101) may control the boost converter (103) based on constant on-time control and may control the inverting buck converter (105) based on peak current control. The rectified AC voltage (VR) may be an AC conductive angle modulated voltage, where the controller (101) may inhibit switching of the inverted buck converter (105) at a dimming frequency having a duty cycle based on a phase angle of the AC conductive angle modulated voltage. ＜img id="iaf01" file="imgaf001.tif" wi="162" he="95" img-content="drawing" img-format="tif" /＞ ＜img id="iaf02" file="imgaf002.tif" wi="136" he="119" img-content="drawing" img-format="tif" /＞

[Walters, Michael M.] 1001 Murphy Ranch Road, Milpitas, CA 95035, US A converter system (100) including a cascade boost converter (103) and inverting buck converter (105) and controller (101) for converting a rectified AC voltage (VR) to a DC output current (ILD). The system uses inductors (L1,L2) and is configured to use a common reference voltage (REF). The controller is configured to control switching of the converters (103,105) in an independent manner to decouple operation from each other. For example, control pulses for the boost converter (103) may be wider than pulses for the buck (104) converter. The controller (101) may control the boost converter (103) based on constant on-time control and may control the inverting buck converter (105) based on peak current control. The rectified AC voltage (VR) may be an AC conductive angle modulated voltage, where the controller (101) may inhibit switching of the inverted buck converter (105) at a dimming frequency having a duty cycle based on a phase angle of the AC conductive angle modulated voltage. ＜img id="iaf01" file="imgaf001.tif" wi="142" he="82" img-content="drawing" img-format="tif" /＞ ＜img id="iaf02" file="imgaf002.tif" wi="124" he="116" img-content="drawing" img-format="tif" /＞

[Hebert, Francois] 1001 Murphy Ranch Road, Milpitas, CA 95035, US A voltage converter includes an output circuit having a high-side device and a low-side device which are formed on a single die (a "PowerDie"). The high-side device (12) includes a lateral diffused metal oxide semiconductor (LDMOS) while the low-side device (14) includes a planar vertical diffused metal oxide semiconductor (VDMOS). The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with, the power die. ＜img id="iaf01" file="imgaf001.tif" wi="147" he="101" img-content="drawing" img-format="tif" /＞

[Alexander Kalnitsky, John M Caruso] 1001 Murphy Ranch Road, Milpitas, CA 95035, US

[Moussaoui, Zaki, Qin, Jifeng, Brazil, Colm] US,Milpitas, CA 95035,1001 Murphy Ranch Road; An EMI reduction network for a converter, the converter including upper and lower power switches provided between an input voltage node and a reference node. An inductance is coupled between the input voltage node and the upper switch at a first node, a capacitance and an auxiliary power switch are coupled in series between the first and reference nodes, and a controller is provided to control switching. The controller switches the upper switch based on a PWM signal. The controller keeps the lower switch turned on until the phase node goes positive while the upper switch is on. The controller turns the auxiliary switch on after the lower power switch is turned off and turns the auxiliary switch off after the upper power switch is turned off. The lower and auxiliary switches may be zero voltage switched, and the upper switch may be zero current switched.

2401 Palm Bay Road N.E. Mail Stop: 53-209 Palm Bay, FL 32905 A method of controlling operation of a wireless device configured in a zero intermediate frequency architecture (200) including a DC loop (347) and a gain loop (345). The method includes processing energy in a wireless medium to generate a corresponding receive signal R, monitoring the receive signal via a predetermined measurement window (RD), detecting a changed condition in the channel, holding the gain feedback control loop at a constant gain level, and operating the DC loop (347) in an attempt to search a stable DC value for the receive signal RD while the gain loop is held constant. A first case is DC saturation (901), where the gain is held constant until DC is controlled. A second case is clear channel assessment, where a prior stored gain setting is applied to the gain loop after detecting the end of the packet (1101). A third case is preparation for receiving an expected acknowledgement packet (1005) after transmitting a packet (1001), where again a prior stored gain setting is applied to the gain loop and DC is searched.

[REES, Theodore, D., ASADA, Akihiro, SMITH, D., Stuart] 1001 Murphy Ranch Road Milpitas, CA 95035;2296 Sun Mor Avenue Mountain View, CA 94040;16-5 Tsutumi Chigasaki-shi;5150 Felter Road San Jose, CA 95132 A hybrid LDD includes a read channel to selectively output a read current, a plurality of write channels, each to selectively output a different write current, and an oscillator channel to selectively output an oscillator current. Additionally, the hybrid LDD includes programmable LDD controller that receives the plurality of enable signals from the external controller, and based on the enable signals, controls timing of the currents output by at least the write channels. The programmable LDD controller can also control timing of the currents output by the read and oscillator channels, based on the enable signals. Further and alternative embodiments are also provided.